Updating of shadow registers in N:1 clock domain

摘要

A processing unit includes a first storage entity being updated at a first clock cycle (CLK1) for holding a master copy of processing unit state. The processing unit further includes at least two shadow storage entities being updated with update information of the first storage entity. A shadow storage entity running at a second clock cycle (CLK2) is slower than the first clock cycle (CLK1). The first storage entity is coupled with the shadow storage entities via an intermediate storage entity, and the intermediate storage entity provides multiple storage stages for buffering consecutive update information of the first storage entity. Selection circuitry is adapted to provide one update information contained in one storage stage to the shadow storage entity with the active clock edge of the second clock cycle (CLK2) in order to update said shadow storage entity.