发明名称 |
DIGITAL CLOCK PLACEMENT ENGINE APPARATUS AND METHOD WITH DUTY CYCLE CORRECTION AND QUADRATURE PLACEMENT |
摘要 |
A digital clock placement engine has circuitry that adjusts a duty cycle of a clock signal and adjusts the locations of the rising/falling edges of the clock signal for purposes of data sampling or other operations. In a forwarded-clock interface implementation, a clock signal is received along with a data signal, and the received clock signal may be distorted to due various factors. To enable the received data signal to be sampled correctly, the clock placement engine generates a recovered clock signal having rising and falling edges that are placed/timed between the rising and falling edges of the received clock signal. |
申请公布号 |
EP2798739(A4) |
申请公布日期 |
2016.08.17 |
申请号 |
EP20110879078 |
申请日期 |
2011.12.29 |
申请人 |
INTEL CORPORATION |
发明人 |
DESAI, JAYEN, J.;FRANCOM, ERIN;PETERS, MATTHEW |
分类号 |
H03K5/156;G11C7/22;H03K5/13;H03K7/08;H03K9/08;H04L7/00 |
主分类号 |
H03K5/156 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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