发明名称 スタック型マルチチップ集積回路の静電気保護
摘要 One feature pertains to a multi-chip module that comprises at least a first integrated circuit (IC) die and a second IC die. The second IC die has an input/output (I/O) node electrically coupled to the first IC die by a through substrate via. The second die's active surface also includes a fuse that is electrically coupled to the I/O node and adapted to protect the second IC die from damage caused by an electrostatic discharge (ESD). In particular, the fuse protects the second IC die from ESD that may be generated as a result of electrically coupling the first die to the second die during the manufacturing of the multi-chip module. Upon coupling the first die to the second die, the fuse may bypass the ESD current generated by the ESD to ground. After packaging of the multi-chip module is complete, the fuse may be blown open.
申请公布号 JP5972473(B2) 申请公布日期 2016.08.17
申请号 JP20150535786 申请日期 2013.10.03
申请人 クアルコム,インコーポレイテッド 发明人 ブライアン・エム・ヘンダーソン;チュウ−グアン・タン;グレゴリー・エー・ウヴィエガーラ;レザ・ジャリリゼインアリ
分类号 H01L21/822;H01L21/3205;H01L21/768;H01L21/82;H01L23/522;H01L25/065;H01L25/07;H01L25/18;H01L27/04 主分类号 H01L21/822
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