发明名称 クロック位相調整回路および受信回路
摘要 PROBLEM TO BE SOLVED: To realize a phase adjustment circuit capable of maintaining high linearity even when an operation frequency is switched.SOLUTION: A clock phase adjustment circuit for adjusting a phase of a fetch clock for fetching an input data signal by a fetch clock of a frequency CLKO N times the frequency of a reference clock CLKI includes: a code conversion circuit 21 for converting a fetch phase adjustment code indicating a phase shift quantity of a fetched input data signal into a reference clock phase adjustment code in accordance with a conversion table; a reference phase adjustment circuit 22 for adjusting the phase of the reference clock accordingly to the phase shift quantity by mixing the reference clock and the reference clock phase adjustment code; and a frequency conversion circuit 23 for converting an adjusted clock into a fetching clock with a frequency of N times.
申请公布号 JP5971102(B2) 申请公布日期 2016.08.17
申请号 JP20120267335 申请日期 2012.12.06
申请人 富士通株式会社 发明人 松本 忠久;田村 泰孝
分类号 H04L7/033 主分类号 H04L7/033
代理机构 代理人
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