发明名称 複数の導電性ポストを平坦化する半導体構造および方法
摘要 Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over the liner and between the posts. A planarized surface is formed which extends across the posts and across one or both of the liner and the fill material. Some embodiments include a semiconductor construction containing a semiconductor die. Electrically conductive posts extend through the die. The posts have upper surfaces above a backside surface of the die, and have sidewall surfaces extending between the backside surface and the upper surfaces. A liner is across the backside surface of the die and along the sidewall surfaces of the posts. Electrically conductive caps are over the upper surfaces of the posts, and have rims along the liner adjacent the sidewall surfaces of the posts.
申请公布号 JP5965537(B2) 申请公布日期 2016.08.10
申请号 JP20150500432 申请日期 2013.02.12
申请人 マイクロン テクノロジー, インク. 发明人 ガンディ,ジャスプリート,エス.
分类号 H01L21/321;H01L21/304;H01L21/3205;H01L21/768;H01L23/522 主分类号 H01L21/321
代理机构 代理人
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