发明名称 情報処理装置、制御回路、制御プログラム、及び制御方法
摘要 The present invention comprises a table control unit (14) which sets a logical address as a retrieval starting position, said logical address satisfying a predetermined condition of storage regions (7a-10a) included in blocks. A logical address selection unit (161) selects a logical address in a prescribed sequence from the retrieval starting position of an address conversion table (18). A physical address acquisition unit (162) acquires a physical address from the address conversion table (18), said physical address corresponding to the selected logical address. A determination unit (163) determines whether to move data which has been stored in the storage region (7a-10a) that represents the acquired physical address. A data movement control unit (17) moves the data in the storage region (7a-10a) that represents the acquired physical address to another storage region (7a-10a). The table control unit (14) updates the physical address associated with the selected logical address in the address conversion table (18) to the physical address that represents the other storage region (7a-10a).
申请公布号 JP5967307(B2) 申请公布日期 2016.08.10
申请号 JP20150522391 申请日期 2013.06.17
申请人 富士通株式会社 发明人 早坂 和美;日下田 雅紀
分类号 G06F12/02;G06F12/00 主分类号 G06F12/02
代理机构 代理人
主权项
地址