发明名称 レジスタレスアーキテクチャによるキャッシュレスマルチプロセッサ
摘要 PROBLEM TO BE SOLVED: To provide a multiprocessor system of high performance and low cost by constructing a multiprocessor system capable of simultaneously accessing a shared memory without using a cache memory.SOLUTION: A shared memory is divided into a plurality of banks, and an individual processor element is connected to each memory bank. The processor element receives an instruction code and an operand from the connected memory bank, transmits an operation result to an adjacent processor element after executing the operation, and makes the operation result a value of an accumulator during the next instruction execution. Since the processor element does not have a register file, data transfer required between processor elements is only the accumulator, a program counter and a small number of control signals. As long as a plurality of processors sequentially execute normal operation instructions, simultaneous read-out accesses to the instruction code and the operand do not collide, and arbitration is required only at a random access time of a shared memory and at a jump instruction execution time.
申请公布号 JP5967646(B2) 申请公布日期 2016.08.10
申请号 JP20120153499 申请日期 2012.07.09
申请人 株式会社エルアミーナ 发明人 田沼 英樹
分类号 G06F9/305;G06F9/32;G06F15/173 主分类号 G06F9/305
代理机构 代理人
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