| 摘要 |
PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor integrated circuit device in which overetching for a memory circuit region isolating layer is suppressed, when etching a logic gate formation layer of the memory circuit region, by preventing the logic gate formation layer of the memory circuit region from remaining.SOLUTION: When a logic gate formation layer 25 remains, as it is, on the periphery of a memory gate 10, reaction gas is produced easily when dry etching the logic gate formation layer 25. Consequently, the logic gate formation layer 25 in a memory circuit region ER1 is removed more accurately, by an automatic endpoint detection method for determining the etching amount, with a change in the reaction gas as a measure.SELECTED DRAWING: Figure 5 |
