发明名称 |
SUCCESSIVE APPROXIMATION RESISTER ANALOG-TO-DIGITAL CONVERTER HAVING SEPARABLE DUAL CAPACITOR ARRAY |
摘要 |
A successive approximation register analog-to-digital converter including separable dual capacitor array is disclosed. The disclosed successive approximation register analog-to-digital converter comprises: a dual capacitor array configured to include a first capacitor array for converting most significant hits of n bits and a second capacitor array for converting least significant bits of the n bits; a comparator configured to compare a level signal outputted from the first capacitor array with a level signal outputted from the second capacitor array; and an SAR logic circuit configured to convert an analog input voltage into a digital signal having the n bits by using the comparison result. Here, the first capacitor array includes a 1-1 capacitor circuit and a 1-2 capacitor circuit and the second capacitor array includes a 2-1 capacitor circuit and a 2-2 capacitor circuit. Each of the capacitor circuits includes capacitors connected in parallel each other. |
申请公布号 |
US2016226507(A1) |
申请公布日期 |
2016.08.04 |
申请号 |
US201515025156 |
申请日期 |
2015.04.09 |
申请人 |
CHUNG-ANG UNIVERSITY INDUSTRY-ACADEMY COOPERATION FOUNDATION |
发明人 |
BAEK Kwang Hyun;CHO Seong Jin;KIM Ju Eon;LEE Chang Woo |
分类号 |
H03M1/38;H03M1/12 |
主分类号 |
H03M1/38 |
代理机构 |
|
代理人 |
|
主权项 |
1. A successive approximation register analog-to-digital converter comprising:
a dual capacitor array configured to include a first capacitor array for converting most significant bits of n bits and a second capacitor array for converting least significant bits of the n bits; a comparator configured to compare a level signal outputted from the first capacitor array with a level signal outputted from the second capacitor array; and an SAR logic circuit configured to convert an analog input voltage into a digital signal having the n bits by using the comparison result, wherein the first capacitor array includes a 1-1 capacitor circuit and a 1-2 capacitor circuit and the second capacitor array includes a 2-1 capacitor circuit and a 2-2 capacitor circuit, and wherein each of the capacitor circuits includes capacitors connected in parallel each other. |
地址 |
Dongjak-gu, Seoul KR |