| 发明名称 |
MEMORY WITH EXTENDED CHARGE TRAPPING LAYER |
| 摘要 |
A memory array includes a plurality of bit lines and a plurality of word lines, a gate region, and a charge trapping layer. The charge trapping layer is wider than a word line; the charge trapping layer is extended beyond the edge of the gate region to facilitate capturing and removing charges. |
| 申请公布号 |
EP2659511(A4) |
申请公布日期 |
2016.08.03 |
| 申请号 |
EP20110853037 |
申请日期 |
2011.12.29 |
| 申请人 |
CYPRESS SEMICONDUCTOR CORPORATION |
发明人 |
FANG, SHENQING;CHEN, TUNG-SHENG;CHEN, CHUN |
| 分类号 |
H01L21/28;H01L27/115;H01L29/423;H01L29/792 |
主分类号 |
H01L21/28 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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