发明名称 決定帰還等化と追跡とのための単一キャリアバースト構造
摘要 Certain aspects of the present disclosure relate to a method for employing a special format for transmitting data blocks which allows parallel equalizations at a receiver. By applying parallel equalization operations, a clock at the receiver can operate at a fraction of the input signal's data rate, which is more practical in the case of very high data rates while power dissipation is also reduced.
申请公布号 JP5964387(B2) 申请公布日期 2016.08.03
申请号 JP20140215640 申请日期 2014.10.22
申请人 クゥアルコム・インコーポレイテッドQUALCOMM INCORPORATED 发明人 イズメイル・ラッキス
分类号 H04B7/005;H04B1/76;H04L27/01 主分类号 H04B7/005
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