LINEAR REGULATOR HAVING HIGH POWER SUPPLY REJECTION RATIO

摘要

The present invention relates to a linear regulator with a high power voltage variation removing ratio. The linear regulator of the present invention includes: a differential amplifier which amplifies an input signal by a predefined amplification ratio; a first amplification unit which includes a first PMOS transistor connected to the output of the differential amplifier and driven by a common source and a second PMOS transistor connected to the output of the first PMOS transistor and driven by the common source; and a second amplification unit which includes a first NMOS transistor connected to the output of the differential amplifier and driven by the common source and a third PMOS transistor connected to the output of the first NMOS transistor and driven by the common source. By doing so, the linear regulator with a high power voltage variation removing ratio of the present invention can be designed with a simple three-stack structure and as a result, the space occupied by the linear regulator in a limited space on a chip can be reduced.