| 摘要 |
PROBLEM TO BE SOLVED: To propose a full adder circuit capable of operating the cumulative addition of a large number of digits and a high speed operation while reducing a circuit scale.SOLUTION: In an asynchronous correlation arithmetic circuit 100, reception data are subjected to two-line encoding by a reception data two-line encoding section 130. The storage value of an addition result storage section 170 is subjected to two-line encoding by an addition result two-line encoding section 180. An asynchronous full addition section 150 adds the output value of the reception data two-line encoding section 130 to the output value of the addition result two-line encoding section 180 with a code corresponding to the output value of a replica data two-line encoding section 140. An overflow detection section 190 detects the occurrence of the overflow of the asynchronous full addition section 150 on the basis of the carrier output of one bit asynchronous full adder of the most significant digit of the asynchronous full addition section 150 and the carrier output of one bit asynchronous full adder of the next lower digit. Then, an overflow counter section 195 adds or subtracts the detection frequency of the overflow detection section 190 in accordance with the value of a code bit for counting. |
