| 摘要 |
PROBLEM TO BE SOLVED: To provide a CMOS semiconductor device having a double-layer SOI structure and an integrated surrounding gate electrode.SOLUTION: A CMOS semiconductor device composed of N-channel and P-channel MIS field effect transistors of a lamination structure comprises: lower layer semiconductor layers (5, 6) provided on a semiconductor substrate 1 via multiple layers of first interlayer insulation films (2, 3); upper layer semiconductor layers (13, 14) provided on a laminated second interlayer insulation film 19; a gate electrode 18 integrated with a structure which surrounds around parts (6, 14) of the lower layer and upper layer semiconductor layers via gate insulation films (16, 17) in a self-alignment manner; and source-drain regions (9, 10, 21, 22, 23, 24) which are provided in parts (5, 13) of the lower layer and upper layer semiconductor layers in a self-alignment manner with the integrated surrounding gate electrode 18 and which have conductivity types different from one another. |
