发明名称 Overlay model for aligning and exposing semiconductor wafers
摘要 A method of calculating an overlay correction model in a unit for the fabrication of a wafer comprising a structural pattern on a substrate and having first overlay marks generated in a first layer and second overlay marks in a second layer. Overlay deviations of a subset of overlay marks are measured providing a subset of overlay model parameters. For a plurality of overlay positions the overlay deviations are estimated using the subset of overlay model parameters. A set of process correction parameters is provided for the plurality of overlay positions. The subset of overlay marks is selected in dependence of the distance to the position of one exposure field, and the selected overlay marks are weighted based on the distance to the overlay position of the exposure field.
申请公布号 EP2620976(B1) 申请公布日期 2016.07.20
申请号 EP20120152483 申请日期 2012.01.25
申请人 QONIAC GMBH 发明人 HABETS, BORIS JOHAN LOUIS
分类号 G03F7/20;G03F9/00 主分类号 G03F7/20
代理机构 代理人
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