| 摘要 |
PURPOSE:To transfer data in FFs (flip-flop) being components of a scan path without skipping one stage of scan FF and one scan FF through the use of a clock for one period by controlling the order of a clock signal to each FF. CONSTITUTION:The order of a clock signal inputted to a scan FF is controlled so that the clock signal (0 1) is inputted to a FF(3e) by 2-input AND gates 8a, 8b and then inputted to a FF(3d). Thus, the order of the input of the clock signal to the FFs being components of the scan path is FF(3f) - FF(3a) without fail. Then the data of the FFs being components of the scan path is transferred by using one period of the clock signal without skipping one stage of scan FF and one scan FF. |
