发明名称 昇圧回路
摘要 A boosting circuit is provided which performs an appropriate boosting operation in accordance with load capacitance. In the boosting circuit, a slope control circuit is provided between a limiter circuit, which limits a high voltage obtained by a charge pump circuit to a desired boosted voltage VPP, and a discharge circuit, which makes the boosted voltage VPP drop quickly to a power supply voltage VCC after the completion of writing, to enable a boosting operation in an appropriate boosted-voltage reach time, by increasing the time taken to reach the boosted voltage VPP in the case where the load capacitance is low, while keeping the time taken to reach the boosted voltage VPP unchanged, irrespective of the presence/absence of the slope control circuit, in the case where the load capacitance is high as in the case of selecting the memory cells collectively.
申请公布号 JP5950636(B2) 申请公布日期 2016.07.13
申请号 JP20120053556 申请日期 2012.03.09
申请人 エスアイアイ・セミコンダクタ株式会社 发明人 村田 正哉;岡 智博
分类号 H02M3/07;H01L21/822;H01L27/04 主分类号 H02M3/07
代理机构 代理人
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