REDUCTION OF INPUT DEPENDENT CAPACITOR DAC SWITCHING CURRENT IN FLASH-SAR ANALOG-TO-DIGITAL CONVERTERS

摘要

Circuits and methods for reducing input dependent capacitor DAC switching current in flash-successive approximation register (SAR) analog-to-digital converters (ADCs) are disclosed. An ADC includes an M-bit flash ADC and N-bit SAR ADC. In flash conversion phase, flash ADC outputs digital signal including most significant M-bits of N-bits of digital output code for a sampled analog signal. SAR ADC includes capacitor DAC and digital engine. The capacitor DAC includes first and second set of capacitors, where first ends of the first and second set of capacitors are coupled to common terminal. The digital engine provides the N-bits of digital output code in SAR conversion phase based on the digital signal and a voltage (Vcom) at the common terminal. During flash conversion phase, second ends of the first set of capacitors are connected to Vref and Vgnd respectively so as to generate a voltage level corresponding to the digital signal as Vcom.

主权项

1. An analog-to-digital converter (ADC) for converting an analog input signal into N-bits of digital output code, the ADC comprising:
an M-bit flash ADC configured to receive a sampled analog signal and to output a digital signal comprising most significant M-bits of the N-bits of digital output code in a flash conversion phase, the sampled analog signal being a stored signal of the analog input signal, M and N being integers; and an N-bit successive approximation register (SAR) ADC comprising:
a capacitor digital-to-analog converter (DAC) comprising a first set of capacitors and a second set of capacitors, each of the first set of capacitors and the second set of capacitors being weighted capacitors such that the capacitors of the first set of capacitors all have respectively different capacitance values and the capacitors of the second set of capacitors all have respectively different capacitance values, first ends of each capacitor of the first set of capacitors and the second set of capacitors coupled to a common terminal; anda digital engine coupled to the M-bit flash ADC and the capacitor DAC for providing the N-bits of digital output code in a SAR conversion phase based on the digital signal and a voltage (Vcom) at the common terminal, the digital engine configured to:
in the flash conversion phase, generate the most significant M-bits of the N-bits of digital output code based on the digital signal received from the M-bit flash ADC, connect second ends of the first set of capacitors to a reference signal (Vref), and connect second ends of the second set of capacitors to a ground reference signal (Vgnd);in a first cycle of the SAR conversion phase, connect second ends of one or more capacitors of the first set of capacitors to the Vgnd if a voltage level corresponding to the digital signal is less than Vref/2, and connect second ends of one or more capacitors of the second set of capacitors to the Vref if the voltage level corresponding to the digital signal is greater than Vref/2 so as to generate the voltage level corresponding to the digital signal as the Vcom; andin subsequent cycles of the first cycle of the SAR conversion phase, control voltage levels at the second ends of the second set of capacitors to perform successive approximation of least significant N-M bits of the N-bits of digital output code based on a SAR conversion algorithm.