IMPLEMENTING CLOCK RECEIVER WITH LOW JITTER AND ENHANCED DUTY CYCLE

摘要

A method and a clock receiver circuit for implementing low jitter and enhanced duty cycle, and a design structure on which the subject circuit resides are provided. The clock receiver circuit accepts single-ended complementary metal oxide semiconductor (CMOS) and differential clock signals. The clock receiver circuit includes input circuitry coupled to a differential pair that biasing a reference clock and allows for single-ended or differential clock signals. The differential pair uses multiple current mirrors for switching the polarity of the input signals to achieve enhanced jitter performance, and cross coupled inverters for retaining signal symmetry.

主权项

1. A method for implementing a clock receiver circuit for implementing low jitter and enhanced duty cycle comprising:
providing an input circuit biasing a reference clock and allowing for single-ended complementary metal oxide semiconductor (CMOS) or differential clock signals; providing the biased single-ended complementary metal oxide semiconductor (CMOS) or differential clock signals coupled to a differential transistor pair; providing a biasing capacitor coupled to said differential transistor pair; providing multiple current mirrors coupled to said differential transistor pair for switching the polarity of input clock signals for enhanced signal performance, and providing cross coupled inverters coupled between said current mirrors for retaining clock signal symmetry.