| 主权项 |
1. A computer program product for analyzing the timing of an integrated circuit, the computer program product comprising:
a netlist reading module for reading a netlist of the integrated circuit, wherein the netlist comprises a beginning point and N terminal points of a clock signal of the integrated circuit and comprises N signal paths each exists between the beginning point and one of the N terminal points, and one transmission line or at least one circuit block exists between the beginning point and each of the N terminal points; a signal path analysis module for analyzing the N signal paths to generate a simplified netlist of the integrated circuit, wherein a first circuit block of the integrated circuit comprises an input terminal for receiving the clock signal and an output terminal for outputting the clock signal, if the input terminal and the output terminal are both coupled with a first signal path of the N signal paths, the signal path analysis module records the first circuit block in the simplified netlist so that a clock delay of the first signal path can be calculated in view of the first circuit block, and if the input terminal is coupled with the first signal path while the output terminal does not couple with the first signal path, the signal path analysis module records an impedance load in the simplified netlist to represent the first circuit block so that the clock delay of the first signal path can be calculated in view of the impedance load instead of the first circuit block; and a clock delay calculating module for calculating N clock delays of the clock signal respectively corresponding to the N signal paths. |
