主权项 |
1. An apparatus to enable efficient transmission of transactions through an interconnect, in a System on a Chip, comprising:
one or more initiator Intellectual Property (IP) cores coupled to the interconnect at one or more initiator ports; one or more target IP cores coupled to the interconnect at two or more target ports, where at least one of the target IP cores may couple to at least two of the target ports; flow logic configured to determine how the interconnect routes transactions between the initiator ports and the target ports; the interconnect includes initiator agents coupled to the initiator ports to receive transaction requests from the initiator IP cores and target agents coupled to the target ports to send transaction requests to the target IP cores; at least one of the initiator agents includes a reorder storage buffer, where the flow logic is configured to allocate storage entries in the reorder storage buffer, where the flow logic is also configured to identify which transactions require storage entries in the reorder storage buffer such that
(i) transaction requests with response ordering dependencies can be sent from the initiator agent to different target ports, such that the transaction requests are concurrently pending,(ii) responses to the transaction requests can be sent by the different target ports in an order that does not match response ordering dependencies required by the transaction requests received from a first initiator IP core,(iii) the reorder storage buffer stores the responses that do not match the response ordering dependencies without preventing the interconnect from delivering any target agent responses, and(iv) the flow logic identifies which transactions require storage entries in the reorder storage buffer operates so as to permit more transaction responses to be pending than can be stored in the reorder storage buffer. |