INGAAS EPI STRUCTURE AND WET ETCH PROCESS FOR ENABLING III-V GAA IN ART TRENCH
摘要
Embodiments of the invention include nanowire and nanoribbon transistors and methods of forming such transistors. According to an embodiment, a method for forming a microelectronic device may include forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer. The multi-layer stack may comprise at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer. The STI layer may be recessed so that a top surface of the STI layer is below a top surface of the release layer. The exposed release layer from below the channel layer by selectively etching away the release layer relative to the channel layer.
申请公布号
WO2016105426(A1)
申请公布日期
2016.06.30
申请号
WO2014US72396
申请日期
2014.12.24
申请人
INTEL CORPORATION
发明人
GARDNER, SANAZ K.;RACHMADY, WILLY;METZ, MATTHEW V.;DEWEY, GILBERT;KAVALIEROS, JACK T.;MOHAPATRA, CHANDRA S.;MURTHY, ANAND S.;RAHHAL-ORABI, NADIA M.;ZELICK, NANCY M.;GHANI, TAHIR