MODEM FOR DATA TRANSMISSION OVER HIGH VOLTAGE DISTRIBUTION LINES

摘要

Modem for data transmission over high voltage distribution lines comprises a block (JADRO) that contains at least two serial communication ports (UART) and at least two ports (I/O) accessible via a connector (PK). The block (JADRO) further comprises a gate array (FPGA), an input analog-digital converter (AD) and an output digital-analog converter (DA). To the gate array (FFGA) a circuit (CPLD) is connected for booting firmware in the memory (RAM) to ensure the required function of the gate array (FPGA) after turning on of the power supply. The circuit (CPLD) is designed to ensure data protection and to check data handling for correctness. The memory (RAM) is connected to the gate array (FPGA) to ensure the entire operation of the gate array (FPGA) program. A memory (FLASH) is also connected to the gate array (FPGA) for saving of internal data. The gate array (FPGA) is equipped with an internal processor (ALU) and has such an internal hardware structure to be able to use the processor (ALU) for the control of processing, reception and transmission of data.