| 摘要 |
Provided are a clock regeneration circuit and a receiver, wherein difference values (V1, V2, V3) from an ideal value can be obtained for respective three sample data (T1, T2, T3) which are obtained by oversampling a 4-level FSK demodulated signal at a higher frequency than that of a symbol clock and in which sample data (T2) at a symbol point (P) is included at a median, and a sampling timing of the symbol point (P) is shifted toward a point where the sample data (T3) having a smaller difference value is obtained, by a time corresponding to the difference value (V2) at the symbol point. Thus, the clock regeneration circuit and the receiver are capable of regenerating a stable clock from multi-level modulated waves in a small calculation amount. |
