发明名称 検証方法、検証プログラムおよび検証装置
摘要 PROBLEM TO BE SOLVED: To easily discriminate between a pseudo error and a true error.SOLUTION: A verification device 1 includes a formation unit 1a for forming evaluation lines 7a-7d to identify whether it is a violation of a verification object on the basis of the shapes of mask patterns 2b-2e including a place in violation of a layout design rule, and a determination unit 1b that determines the presence or absence of interference of the evaluation lines 7a-7d formed by the formation unit 1a, and outputs the determination results.
申请公布号 JP5942442(B2) 申请公布日期 2016.06.29
申请号 JP20120016468 申请日期 2012.01.30
申请人 富士通セミコンダクター株式会社 发明人 須川 一弥;土井 一正;鈴木 浩一;宮内 徹;峯村 雅彦
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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