| 摘要 |
A chip scale package and a method for fabrication thereof. The chip scale package 100 comprises a substrate 1 with a contact pad 2 at a first main surface 3, a flexible interconnect structure 45 and a bonding structure 10. The flexible interconnect structure 45 comprises a first dielectric layer 4 on top of the first main surface 3 of the substrate 1. A first via 5 electrically contacts the contact pad 2. The first via 5 extends from the contact pad 3 through the first dielectric layer 4 to a first planar upper main surface 11 of the first dielectric layer 4. The flexible interconnect structure 45 further comprises a planar metal spring 6 on top of the first planar upper main surface 11 electrically contacts the first via 5, at a first end 12 of the planar metal spring 6. The flexible interconnect structure 45 further comprises a second dielectric layer 7 on top of the first dielectric layer 4, and a second via 8 electrically contacts the planar metal spring 6, at a second end 13 of the planar metal spring 6. The second dielectric layer 7 covers the planar metal spring 6. The second via 8 extends from the planar metal spring 6 through the second dielectric layer 7 to a second planar upper main surface 14 of the second dielectric layer 7. The flexible interconnect structure 45 further comprises a second metal 9 on top of the second planar upper main surface 14. The second metal 9 electrically contacts the second via 8. A bonding structure 10 on top of the flexible interconnect structure 45, electrically contacts the second metal 9. The first and second dielectric layers 4,7 of the flexible interconnect structure 45 have an elastic modulus below 200MPa. |
