发明名称 比較回路およびA/D変換回路
摘要 A comparator includes: a differential amplifier of which operational state is switched in response to a clock-signal, and which outputs a first intermediate-output corresponding to a first input-signal and a second intermediate-output corresponding to a second input-signal; a differential latch circuit of which operational state is switched in response to the clock-signal, and a state of which is changed depending on the first intermediate-output and the second intermediate-output; a first adjuster configured to adjust a threshold of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output; and a second adjuster configured to adjust a threshold variation of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output.
申请公布号 JP5942798(B2) 申请公布日期 2016.06.29
申请号 JP20120248579 申请日期 2012.11.12
申请人 富士通株式会社 发明人 檀上 匠
分类号 H03K5/08;H03M1/36 主分类号 H03K5/08
代理机构 代理人
主权项
地址