| 摘要 |
The present technology relates to an etching method for a gate stack capable of realizing a high etching selection ratio to other materials during the etching process of a highly-dielectric material. According to the present technology, the etching method for a gate stack is applied to a highly-dielectric material layer on a substrate and an upper layer on the highly-dielectric material layer and includes: a first etching process performing step of etching the upper layer to form an upper layer pattern; a step of forming a spacer on the side wall of the upper layer pattern; and a second etching process performing step of etching the highly-dielectric material layer using the plasma of main etching gas and additional gas. In the second etching process, the amount of the additional gas can be maintained as the same as the amount of the main etching gas to raise the etching selection ratio to the substrate. |
