| 摘要 |
A variable frequency divider is arranged to divide a frequency of an incoming signal by a variable number D to provide a resultant signal. The arrangement comprises: a first counter 108 having a first clock input and an output undergoing a single cycle for P cycles of the first clock if a first control input is in a first state, or undergoing a single cycle for P+1 cycles of the first clock if the first control input is in a second state; a second counter 110 with a second clock input clocked by the output of the first counter 108 and having a second output undergoing a single cycle for N second clock cycles, wherein N is an integer predetermined by a second control input; and a controller 112 arranged to determine the first and second control inputs such that the first control input is in said second state for a number A of first clock cycles such that D=N•P+A and wherein the controller 112 selects N and A such that the resultant signal has cumulative high and low times which are the same to within half a cycle of said second clock input. |
