| 摘要 |
The present invention relates to a delay locked loop circuit. The delay locked loop circuit comprises: a clock delay unit for generating an internal clock by delaying an external clock by a delay time required for delay-locking; a single-to-differential divider for generating multi-phase divided clocks which are generated at a specific edge of the internal clock by the internal clock as a source clock; and a phase correction unit for correcting a phase error between the multi-phase divided clocks. Therefore, the delay locked loop circuit can accurately generate multi-phase clocks by reducing offset between the multi-phase clocks. |
