| 发明名称 |
DUTY CYCLE DETECTION CIRCUIT AND METHOD |
| 摘要 |
A duty cycle detection circuit may include: a timing signal generation unit to generate a plurality of timing signal groups by selectively combining multi-phase clock signals according to an enable signal; and a detection unit to generate a duty detection signal by selectively combining signals of the plurality of timing signal groups according to the enable signal. |
| 申请公布号 |
US2016182019(A1) |
申请公布日期 |
2016.06.23 |
| 申请号 |
US201514625868 |
申请日期 |
2015.02.19 |
| 申请人 |
SK hynix Inc. |
发明人 |
SEO Young Suk;IM Da In |
| 分类号 |
H03K3/017;H03K3/012 |
主分类号 |
H03K3/017 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A duty cycle detection circuit comprising:
a timing signal generation unit to generate a plurality of timing signal groups by selectively combining multi-phase clock signals according to an enable signal; and a detection unit to generate a duty detection signal by selectively combining signals of the plurality of timing signal groups according to the enable signal. |
| 地址 |
Icheon-si Gyeonggi-do KR |
