发明名称 UPDATING PERSISTENT DATA IN PERSISTENT MEMORY-BASED STORAGE
摘要 A processor includes a processing core to execute an application including instructions encoding a transaction with a persistent memory via a volatile cache that includes a cache line associated with the transaction, the cache line being associated with a cache line status, and a cache controller operatively coupled to the volatile cache, the cache controller, in response to detecting a failure event, to, in response to determining that the cache line status that the cache line is committed, evict contents of the cache line to the persistent memory, and in response to determining that the cache line status indicating that the cache line is uncommitted, discard the contents of the cache line.
申请公布号 US2016179687(A1) 申请公布日期 2016.06.23
申请号 US201414579934 申请日期 2014.12.22
申请人 Intel Corporation 发明人 KUMAR SANJAY;SANKARAN RAJESH;DULLOOR SUBRAMANYA;LI SHENG
分类号 G06F12/08;G06F3/06 主分类号 G06F12/08
代理机构 代理人
主权项 1. A processor comprising: a processing core to execute an application comprising instructions encoding a transaction with a persistent memory via a volatile cache, wherein the volatile cache comprises a cache line associated with the transaction, the cache line being associated with a cache line status; and a cache controller operatively coupled to the volatile cache, the cache controller, in response to detecting a failure event, to: in response to determining that the cache line status indicates that the cache line is committed, evict contents of the cache line to the persistent memory, andin response to determining the cache line status indicates that the cache line is uncommitted, discard the contents of the cache line.
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