| 发明名称 |
INSTRUCTION AND LOGIC FOR SUPPRESSION OF HARDWARE PREFETCHERS |
| 摘要 |
A processor includes a core, a hardware prefetcher, and a prefetcher control module. The hardware prefetcher includes logic to make speculative prefetch requests, through a memory subsystem, for elements for execution by the core, and logic to store prefetched elements in a cache. The prefetcher control module includes logic to selectively suppress, based on a hardware-prefetch suppression instruction executed by the core, a speculative prefetch request to be made by the hardware prefetcher. |
| 申请公布号 |
US2016179544(A1) |
申请公布日期 |
2016.06.23 |
| 申请号 |
US201414580999 |
申请日期 |
2014.12.23 |
| 申请人 |
Heinecke Alexander F.;Hughes Christopher J.;Kim Daehyun;Park Jong Soo |
发明人 |
Heinecke Alexander F.;Hughes Christopher J.;Kim Daehyun;Park Jong Soo |
| 分类号 |
G06F9/38;G06F9/30 |
主分类号 |
G06F9/38 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A processor, comprising:
a core; a hardware prefetcher, including:
a first logic to make speculative prefetch requests, through a memory subsystem, for elements for execution by the core; anda second logic to store prefetched elements in a cache; and a prefetcher control module, including:
a third logic to selectively suppress, based on a hardware-prefetch suppression instruction executed by the core, a speculative prefetch request to be made by the hardware prefetcher. |
| 地址 |
San Jose CA US |
