REDUCING SOLDER PAD TOPOLOGY DIFFERENCES BY PLANARIZATION

摘要

A technique is disclosed for causing the top surfaces of solder bumps on a chip to be in the same plane to ensure a more reliable bond between the chip and a substrate. The chip is provided with solder pads that may have different heights. A dielectric layer is formed between the solder pads. A relatively thick metal layer is plated over the solder pads. The metal layer is planarized to cause the top surfaces of the metal layer portions over the solder pads to be in the same plane and above the dielectric layer. A substantially uniformly thin layer of solder is deposited over the planarized metal layer portions so that the top surfaces of the solder bumps are substantially in the same plane. The chip is then positioned over a substrate having corresponding metal pads, and the solder is reflowed or ultrasonically bonded to the substrate pads.

主权项

1. A method comprising:
providing an electronic device with a first surface and a second surface opposite the first surface; providing a first solder pad at a first distance above the first surface and a second solder pad at second distance above the first surface, the first distance being different from the second distance; providing a dielectric layer between the first solder pad and the second solder pad; plating a first metal layer portion over the first solder pad above a height of the dielectric layer; plating a second metal layer portion over the second solder pad above the height of the dielectric layer; planarizing the first metal layer portion and the second metal layer portion so as to have a third and a fourth surface respectively, wherein the third surface and the fourth surface are in the same plane; depositing a first solder layer over the first metal layer portion; and depositing a second solder layer over the second metal layer portion, such that a top surface of the first solder layer is in the same plane as a top surface of the second solder layer.