Transistor Plasma Charging Eliminator

摘要

A computer-implemented method capable of minimizing a plasma-induced charging effect to a transistor in a plasma-based process is provided. The plasma-based process is for a dielectric layer on the transistor and a metal layer is formed above the dielectric layer. The method may include calculating difference in potential between a gate terminal and a remaining terminal of the transistor, and determining whether an absolute value of the potential at the gate terminal is larger than an absolute value of the potential at the remaining terminal and the difference in potential between the gate terminal and the remaining terminal exceeds a degradation threshold.

主权项

1. A computer-implemented method capable of minimizing a plasma-induced charging effect to a transistor in a plasma-based process for a dielectric layer performed above the transistor on which a metal layer is formed, comprising:
calculating difference in potential between a gate terminal and a remaining terminal of the transistor; and determining whether an absolute value of the potential at the gate terminal is larger than an absolute value of the potential at the remaining terminal and the difference in potential between the gate terminal and the remaining terminal exceeds a degradation threshold.