发明名称 |
SIMULTANEOUS INVALIDATION OF ALL ADDRESS TRANSLATION CACHE ENTRIES ASSOCIATED WITH X86 PROCESS CONTEXT IDENTIFIER |
摘要 |
A translation-lookaside buffer (TLB) includes a plurality of entries, wherein each entry of the plurality of entries is configured to hold an address translation and a local valid bit vector, wherein each bit of the local valid bit vector is mapped from a different value of an x86 instruction set architecture (ISA) process context identifier (PCID). The TLB also includes an input that receives an invalidation bit vector having bits corresponding to the bits of the local valid bit vector of the plurality of entries. The TLB also includes logic that simultaneously invalidates a bit of the local valid bit vector of each entry of the plurality of entries that corresponds to a set bit of the invalidation bit vector. |
申请公布号 |
US2016179688(A1) |
申请公布日期 |
2016.06.23 |
申请号 |
US201414890341 |
申请日期 |
2014.11.26 |
申请人 |
VIA ALLIANCE SEMICONDUCTOR CO., LTD. |
发明人 |
EDDY COLIN |
分类号 |
G06F12/08;G06F15/78;G06F12/10 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
1. A translation-lookaside buffer (TLB), comprising:
a plurality of entries, wherein each entry of the plurality of entries is configured to hold an address translation and a local valid bit vector; wherein each bit of the local valid bit vector is mapped from a different value of an x86 instruction set architecture (ISA) process context identifier (PCID); an input that receives an invalidation bit vector having bits corresponding to the bits of the local valid bit vector of the plurality of entries; and logic that simultaneously invalidates a bit of the local valid bit vector of each entry of the plurality of entries that corresponds to a set bit of the invalidation bit vector. |
地址 |
Shanghai CN |