发明名称 |
METHOD AND APPARATUS FOR PERFORMING A VECTOR BIT REVERSAL AND CROSSING |
摘要 |
An apparatus and method for performing a vector bit reversal and crossing. For example, one embodiment of a processor comprises: a first source vector register to store a first plurality of source bit groups, wherein a size for the bit groups is to be specified in an immediate of an instruction; a second source vector to store a second plurality of source bit groups; vector bit reversal and crossing logic to determine a bit group size from the immediate and to responsively reverse positions of contiguous bit groups within the first source vector register to generate a set of reversed bit groups, wherein the vector bit reversal and crossing logic is to additionally interleave the set of reversed bit groups with the second plurality of bit groups; and a destination vector register to store the reversed bit groups interleaved with the first plurality of bit groups. |
申请公布号 |
US2016179529(A1) |
申请公布日期 |
2016.06.23 |
申请号 |
US201414581738 |
申请日期 |
2014.12.23 |
申请人 |
INTEL CORPORATION |
发明人 |
CORBAL JESUS;OULD-AHMED-VALL ELMOUSTAPHA;VALENTINE ROBERT;CHARNEY MARK J. |
分类号 |
G06F9/30 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
1. A processor comprising:
a first source vector register to store a first plurality of source bit groups, wherein a size for the bit groups is to be specified in an immediate of an instruction; a second source vector to store a second plurality of source bit groups; vector bit reversal and crossing logic to determine a bit group size from the immediate and to responsively reverse positions of contiguous bit groups within the first source vector register to generate a set of reversed bit groups, wherein the vector bit reversal and crossing logic is to additionally interleave the set of reversed bit groups with the second plurality of bit groups; and a destination vector register to store the reversed bit groups interleaved with the first plurality of bit groups. |
地址 |
Santa Clara CA US |