DIGITAL PHASE CONTROLLED DELAY CIRCUIT

摘要

An adjustable phase clock generator circuit is described that may include a DLL and a phase adjustor to further adjust the phase of a selected clock phase from the DLL. Both the DLL and phase adjustor may be formed from current starved delay elements that are biased from a common bias generator circuit.

主权项

1. An adjustable phase clock generator circuit, comprising:
a bias generator; a Delay Locked Loop (DLL) having two or more delay elements to be biased from the bias generator, wherein the DLL further has an output to provide a selected clock with a selected phase; and a phase adjustor coupled to the DLL output to adjust the phase of the selected clock and to provide the phase-adjusted clock at an output, the phase adjustor including at least one delay element that is at least partially biased from the bias generator.