MEMORY WITH MULTIPLE WRITE PORTS

摘要

A memory 2 includes a regular array of storage elements 4. A regular array of write multiplexers 8 is provided outside of the regular array of storage elements 4. The storage element pitch is matched to the write multiplexer pitch. The write multiplexers 10 support a plurality of write ports. When forming a memory design 2, a given instance of an array of write multiplexers 8 may be selected in dependence upon the desired number of write ports to support and this combined with a common form of storage element array 4.

主权项

1. A memory comprising:
a regular array of storage elements; and a regular array of write multiplexers, each write multiplexer to select from among a plurality of bit lines an active bit line to write write data to a selected storage element within said regular array of storage elements, wherein said write multiplexer connects said active bit line to a precharged node and, in dependence upon an asserted write word line, said write multiplexer applies a corresponding bit line value to the precharged node.