发明名称 Low Power Verification Method for a Circuit Description and System for Automating a Minimization of a Circuit Description
摘要 A method for low power verification of a circuit description comprises minimizing a circuit description by creating a plurality of crossover trees, and evaluating each of the plurality of crossover trees to identify circuit description errors, in particular low power circuit description errors. The minimizing may comprise creating a plurality of crossover trees to represent circuit description, wherein each crossover tree has a unique set of selected ports and gates of the circuit description.
申请公布号 US2016180012(A1) 申请公布日期 2016.06.23
申请号 US201414909018 申请日期 2014.07.23
申请人 SYNOPSYS, INC. 发明人 Senapati Dipti Ranjan;De Kaushik;Mukherjee Rajarshi;Ramachandra Shreedhar
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项 1. . A computer-implemented method for low power verification of a circuit description corresponding to a circuit design for manufacture, the method comprising: minimizing the circuit description by creating a plurality of crossover trees; and evaluating each of the plurality of crossover trees to identify low power errors in the circuit description.
地址 Mountain View CA US