Optimization Of Parasitic Capacitance Extraction Using Statistical Variance Reduction Technique

摘要

A method for performing parasitic capacitance extraction of an integrated circuit (IC) design includes: defining a Gaussian surface around an origin net of the IC design; partitioning the Gaussian surface into a plurality of regions; performing an initial plurality of random walks from each region using a Monte Carlo field solver; and dynamically allocating an additional plurality of random walks among the plurality of regions, wherein the allocation is based on statistical errors associated with the initial plurality of random walks for each of the regions. Results from the random walks are averaged to estimate parasitic capacitance of the origin net. The method may include performing the random walks for each region in pairs, wherein a first random walk of the pair is selected in accordance with an anti-symmetric probability function, and a second random walk of the pair is antithetic to the first random walk of the pair.

主权项

1. A computer readable medium that stores instructions, which, when executed, cause a computer to perform a method of performing parasitic capacitance extraction of an integrated circuit (IC) design comprising:
defining a Gaussian surface around an origin net of the IC design; partitioning the Gaussian surface into a plurality of regions; using a Monte Carlo field solver, performing an initial plurality of random walks from each region, wherein each of the initial plurality of random walks ends on a conductor of the IC design; dynamically allocating an additional plurality of random walks among the plurality of regions, wherein a number of the additional plurality of random walks allocated to each region is based on a statistical error associated with the initial plurality of random walks performed from the region; and summing results of random walks performed from each of the regions to estimate a parasitic capacitance of the origin net.