LIGHTWEIGHT RESTRICTED TRANSACTIONAL MEMORY FOR SPECULATIVE COMPILER OPTIMIZATION

摘要

Embodiments described herein utilize restricted transactional memory (RTM) instructions to implement speculative compile time optimizations that will be automatically rolled back by hardware in the event of a missed speculation. In one embodiment, a lightweight version of RTM for speculative compiler optimization is described to provide lower operational overhead in comparison to conventional RTM implementations used when performing SLE.

主权项

1. A processing apparatus comprising:
decode logic to decode a first instruction into a decoded first instruction, the decoded instruction including a first operand; and an execution unit to execute the first decoded instruction to begin a transactional execution mode, wherein the transactional execution mode to cause the apparatus to set a write attribute associated with transactional memory in response to a speculative store instruction and to not set a read attribute associated with the transactional memory in response to a speculative load instruction, wherein the speculative load instruction and the speculative store instruction execute while the apparatus is in the transactional execution mode.