INSTRUCTION AND LOGIC TO PERFORM A FUSED SINGLE CYCLE INCREMENT-COMPARE-JUMP

摘要

In one embodiment a binary translation is used to fuse multiple macroinstructions of an instruction set architecture into a single macroinstruction. Fusible instruction sequences include a sequence of increment, compare, and jump instructions. In one embodiment, a processing device provides support for the fused macroinstruction. In one embodiment, the processing device executes the fused macroinstruction within a single execution stage of a processor pipeline. In one embodiment, the fused macroinstruction is performed within a single execution cycle.

主权项

1. A processing apparatus comprising:
decode logic to decode a fused instruction into a decoded fused instruction including a first operand and a second operand; and an execution unit to execute the fused decoded instruction to perform increment, compare, and jump operations as a single machine-level macroinstruction.