| 摘要 |
A cache stores 2ΛJ-byte cache lines has an array of 2ΛN sets each holds tags each X bits and 2∧W ways. An input receives a Q-bit address, MA[(Q-1):0], having a tag MA[(Q-1):(Q-X)] and index MA[(Q-X-1):J]. Q is at least (N+J+X-l). Set selection logic selects one set using the index and tag LSB; comparison logic compares all but the LSB of the tag with all but the LSB of each tag in the selected set and indicates a hit if a match; allocation logic, when the comparison logic indicates there is not a match: allocates into any of the 2ΛW ways of the selected set when operating in a first mode; and into a subset of the 2ΛW ways of the selected set when operating in a second mode. The subset of is limited based on bits of the tag portion. |
