发明名称 電圧トランジェント抑制回路
摘要 PROBLEM TO BE SOLVED: To enable suppressing lowering of a bus voltage to a large transient load by adding a small-capacitance capacitor and a small-sized circuit and to enable providing further excellent bus-voltage characteristics to a load.SOLUTION: A voltage transient suppression circuit 30 is connected to a bus that connects a power-supply system 10 including a battery 14 and a load 20, and includes: a capacitor 31 connected to be chargeable by power from the power-supply system and connected to the bus between the power-supply system and the load; a bus-voltage detection circuit 35 detecting lowering of a bus voltage; and connection control means connecting a negative electrode of the capacitor to a positive electrode of the battery on the basis of the detection result of the bus-voltage detection circuit. The connection control means prevents the bus voltage from lowering to a battery voltage by connecting the capacitor to the battery to discharge in receiving an output of the bus-voltage detection circuit that is outputted when the bus voltage falls below a predetermined control-operation threshold value.
申请公布号 JP5939634(B2) 申请公布日期 2016.06.22
申请号 JP20120155185 申请日期 2012.07.11
申请人 NECスペーステクノロジー株式会社 发明人 権代 智丈;吉田 禎仁
分类号 H02J1/00;G05F1/10;H02J7/00;H02J7/34 主分类号 H02J1/00
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