| 摘要 |
An All-Digital-Phase-Locked-Loop, ADPLL, arranged for generating a DCO output signal and a feedback loop comprising a set of components for controlling the DCO. The components comprising a Time-to-Digital Converter provided for performing phase detection within a predetermined observation window between a reference signal and an enable signal, a first subset of components arranged for generating the enable signal from the DCO output signal, and a second subset of components arranged for positioning the reference signal within the predetermined observation window. The first subset of components comprises a multiphase generator unit deriving from the DCO output signal a plurality of phase-shifted DCO copies and a phase selection unit for selecting on the basis of the phase setting control signal a DCO copy having an appropriate phase-shift for generating the enable signal. The DTC of the second subset of components has a reduced range with respect to that of the period of the multiphase generator output signals over at least part of the frequency range of the DCO. |
