发明名称 |
DECREASING THE CRITICAL DIMENSIONS IN INTEGRATED CIRCUITS |
摘要 |
A method (100) for lithographic patterning of a substrate is described. The method comprises obtaining a substrate to be patterned. It furthermore comprises subsequently applying at least twice the following cycle : applying a lithographical patterning process of a thermally shrinkable metal-oxide layer for forming a metal-oxide pattern, and thermally shrinking the metal-oxide pattern. The different metal oxide patterns formed during the at least two cycles are outlined relatively with respect to each other so that the shrunk metal-oxide patterns form together an overall pattern to be transferred to the substrate. After said applying at least twice the cycle, the overall pattern is transferred to the substrate. |
申请公布号 |
EP3035120(A2) |
申请公布日期 |
2016.06.22 |
申请号 |
EP20150201423 |
申请日期 |
2015.12.18 |
申请人 |
IMEC VZW;KATHOLIEKE UNIVERSITEIT LEUVEN |
发明人 |
ALTAMIRANO SANCHEZ, EFRAIN;YASIN, FARRUKH QAYYUM;DEMEYER, RAVEN |
分类号 |
G03F7/00;G03F7/40;H01L21/00 |
主分类号 |
G03F7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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