| 摘要 |
Provided are a skippable one-bit full adder and field-programmable gate array (FPGA)<b/>device, comprising: a first multiplexer, a second multiplexer and an adder; the first multiplexer comprises a first addend input terminal and a first constant input terminal, the first constant input terminal being configured to input a first constant to the first multiplexer; the second multiplexer comprises a second addend input terminal and a second constant input terminal, the second constant input terminal being configured to input a second constant to the second multiplexer; and when the first addend input terminal is not used to input a first addend, and/or the second addend input terminal is not used to input a second addend, the first multiplexer selects and outputs the first constant inputted by the first constant input terminal, and the second multiplexer selects and outputs the second constant inputted by the second constant input terminal, enabling a carry output terminal of the adder to generate an adder carry output signal determined according to the first constant and the second constant. |
