发明名称 記憶制御装置、記憶装置、情報処理システム、および、それらにおける処理方法
摘要 There is provided a memory control apparatus including: a pre-read processing section reading pre-read data from a data area to be written to before a write process in a predetermined data area of a memory cell array; a conversion determination section which, upon selectively allowing the pre-read data to transition to either a first conversion candidate or a second conversion candidate of the write data to be written in the write process, generates a determination result for selecting either of the candidates based on the larger of two values of which one is the number of bits transitioning from the first value to the second value and of which the other is the number of bits transitioning from the second value to the first value; and a conversion control section selecting either of the candidates in accordance with the determination result.
申请公布号 JP5929790(B2) 申请公布日期 2016.06.08
申请号 JP20130048776 申请日期 2013.03.12
申请人 ソニー株式会社 发明人 石井 健;筒井 敬一;藤波 靖;中西 健一;足立 直大;大久保 英明;新橋 龍男
分类号 G11C13/00 主分类号 G11C13/00
代理机构 代理人
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