| 发明名称 |
TIME-TO-DIGITAL CONVERTER USING STOCHASTIC PHASE INTERPOLATION |
| 摘要 |
Provided is a time-to-digital converter. The time-to-digital converter includes several delay circuits, an adder configured to count outputs of the delay circuits, and a least significant bit (LSB) truncation circuit configured to truncate a predetermined number of LSBs from a result output by the adder. The time-to-digital converter is configured to determine a time interval between a start signal and a stop signal within one cycle of a clock having a predetermined period. |
| 申请公布号 |
US2016156362(A1) |
申请公布日期 |
2016.06.02 |
| 申请号 |
US201514817727 |
申请日期 |
2015.08.04 |
| 申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KIM SUNG-JIN;Kim Jihyun;Kim Taeik |
| 分类号 |
H03L7/189;G04F10/00 |
主分类号 |
H03L7/189 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A time-to-digital converter, comprising:
a plurality of delay circuits; an adder configured to count outputs of the delay circuits; and a least significant bit (LSB) truncation circuit configured to truncate a predetermined number of LSBs from a result output by the adder, wherein the time-to-digital converter is configured to determine a time interval between a start signal and a stop signal within one cycle of a clock signal having a predetermined period. |
| 地址 |
Suwon-si KR |
